A low-voltage low-distortion MOS sampling switch

In order to reduce distortion due to variation of the gate overdrive and the threshold voltage, a novel low-voltage constant-resistance sampling switch is proposed. The technique to reduce nonlinearity can be used in a high resolution sample-and-hold circuit. TSMC 0.18 /spl mu/m standard CMOS technology is used. Results indicate that much lower total harmonic distortion (THD) is achieved by the proposed circuit. The low THD meets the requirements in the application of low-voltage low-distortion switched-capacitor circuits.