Biasing techniques for subthreshold MOS resistive grids

A classic resistive network implemented using MOS transistors suffers from nonlinearity in the subthreshold exponential parameter /spl kappa/ that arises due to varying V/sub GB/ and V/sub BS/. We show two biasing techniques that alleviate these effects. The first technique always uses transistors with constant gate-to-bulk voltage. The second technique uses a novel bulk-to-source biasing scheme to ensure zero bulk-to-source voltage. We propose a PMOS spatial filtering circuit that employs this scheme to extend the range of linearity of subthreshold resistive networks. Measured experimental results from a 1.5um CMOS process show that our spatial filtering circuit has less than 5% variation in space-constant over a measured 94dB (100fA-5nA) dynamic range as opposed to a conventional spatial filtering circuit, which for the same variation has a measured dynamic range of less than 80dB (100fA-1nA). Our techniques should be useful in translinear MOS circuits where linear operation over a wide dynamic range of input currents is important.