A low current consumption CMOS latched comparator for body-implanted chip

The paper presents a very low-current consumption latched comparator, for use in a medical application, as a component of a delta-sigma (/spl Delta//spl Sigma/) modulator, which takes advantage of the low gate-source voltage by operating in the sub-threshold region. The comparator has been designed using 0.35-/spl mu/m standard CMOS technology, operating with a 1.5 V power supply. The current consumption of the comparator achieved was less than 150 nA in a post-layout simulation.