Heap charge pump optimisation by a tapered architecture

The heap charge pump represents an attractive voltage multiplier scheme in integrated circuits where only low-voltage devices are available. The paper presents a performance optimisation of the heap charge pump achieved by using a tapered architecture. The proposed optimisation allows improvements on the order of 30% in terms of maximum output voltage as compared to the conventional heap charge pump. A mathematical description of both the conventional and the proposed structure was developed. MATLAB/sup /spl reg//-based simulation results demonstrate the effectiveness of the proposed scheme.