A low power decimation filter architecture for high-speed single-bit sigma-delta modulation

A novel architecture, suitable for high-speed FIR decimation filters for single-bit sigma-delta modulation, is proposed. By using efficient data and coefficient representation, the total number of partial products is reduced, leading to low power consumption. The work focuses on filters whose design is based on cascaded comb filters, although the approach is applicable to any FIR filter.