A 1.2 V sense amplifier for high-performance embeddable NOR flash memories

This paper presents a sense amplifier scheme for low-voltage embeddable NOR flash memory applications. The architecture of the proposed sense amplifier is based on a folded cascode configuration which allow the bit-line voltage to be regulated even in the case of a power supply of about 1.08 V. The proposed scheme was designed using low-leakage transistors for a 0.13-/spl mu/m flash CMOS technology. Simulation showed a read time of 16 ns and 11 ns for the worst-case and the best-case condition, respectively.