Class-AB rail-to-rail CMOS analog buffer

In this paper, a low-power rail-to-rail CMOS analog buffer is presented. The circuit is based on an input stage made up of two complementary class AB differential pairs, while a simple additional circuit allows rail-to-rail operation at the output terminal. The proposed circuit combines low static power consumption and high drive capability, hence is very suitable for applications with large capacitive loads. The buffer has been designed in a 0.35-/spl mu/m CMOS technology to operate with a /spl plusmn/1.5 V dual supply. Simulated results are provided in order to demonstrate the proper operation of the proposed circuit. A rail-to-rail signal swing is achieved and a THD lower than -44 dB is obtained for a 2.4-V/sub pp/ 100-kHz input sinewave signal, whereas the input capacitance is lower than 32 fF.