A high-resolution time digitizer utilizing dual PLL circuits

A new architecture for a high-resolution time digitizer has been studied. It utilizes dual PLL circuits that generate two slightly different delays. By using time difference of these delays, a high-resolution time digitizer can he composed. A test chip was fabricated with a CMOS 0.18 /spl mu/m technology in the VDEC multi-project LSI service to confirm this concept. Each PLL has 16-stages ring oscillator. A PLL oscillates at 170 MHz, and the other PLL oscillates at 160 MHz by using same reference clock. To compose ring oscillator with even number of stages, an asymmetric ring oscillator, which was previously developed by us, is used. Time measurement is done in 3 ranges; coarse, fine, and super-fine time. Coarse time is measured with a counter of the 170 MHz clock. Fine time is measured with 16 phase taps from the 170 MHz oscillator. Super-fine time measurement is done with two lines of delay elements. Time resolutions of each ranges differ by a factor of 16, and the resolution of the super-fine time will be 23 ps/bit. Circuit concept, simulation results and a test chip fabrication are described.