PASIC. A sensor/processor array for computer vision

The PASIC prototype chip contains 256*256 photosensors, a linear array of 256 A/D converters, two 256 8-bit shift registers, 256 bit-serial processors, and a 256*256 bit dynamic RAM. It appears to be a viable architecture for low-level vision processing. The processors operate in SIMD model at 20 MHz. To avoid high speed transfer of analog data, an A/D converter in the form of a linear array of comparators is used. The architecture of the processing part conforms to the row parallel output from the A/D-converters. A simple but efficient processor excellently suited to the special VLSI constraints of the sensor was designed. The pitch in the present version of PASIC is 30 mu m and it was possible to fit the A/D-converter circuitry, the shift register, the ALU, and the memory into this narrow slot. A key factor is the unified structure achieved by extending the memory data bus to all other units within the same column. The versatility of the chip is shown using three algorithms: edge detection, shading correction, and histogram-based thresholding. Each is executed in approximately 10 ms.<
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