MD16: DSP with some RISC features for embedded system

To achieve the high performance/cost ratio, the idea of combining the advantages of DSP and RISC in a single architecture is a solution for the booming and versatile embedded application systems. The existent methods that appear in many literatures all focus on the construction of mixed architecture with RISC basement. Contrary to the above, a new idea of constructing architecture with DSP basement and supplementing it with some RISC features is put up in this paper. It can exert the advantages of DSP architecture by instruction level parallelization and powerful memory access capability, and obtain RISC good high-level language support by the manners of local-homogenous register set and RISC-like pipeline. To accelerate the DSP design and optimize the system, integrated design system (IDS) is presented to complete the hardware/software co-design and co-validation. Application programs can also be rapidly developed based on the integrated development environment (IDF). The behavior level simulation of the DSP system has been completed. It is given as 150 MIPS under the condition of 0.18 /spl mu/m technology library. FPGA validation is also accomplished.