Characterization and model of on-chip flicker noise with deep Nwell (DNW) isolation for 130nm and beyond SOC

An investigation of the flicker noise, by exploring 0.13 /spl mu/m and beyond MS/RF CMOS technology, was carried out for wireless system-on-a-chip (SOC) applications. The on-chip flicker noise of various components are characterized and accurately modeled. The feasibility of deep N-well isolation to suppress substrate coupling of analog nodes from digital clock noise is also demonstrated.