Simple modeling expressions for substrate network of on-chip inductors

Simple monomial expressions to determine the values of the components in the substrate network of a new on-chip inductor model are proposed. The expressions are given in terms of geometry parameters to be useful for the physical design of the layout. We have evaluated the accuracy of our expressions with a 3D field solver as well as comparisons with measured results. Inductors were fabricated using a 0.35 mum CMOS process as well as a 0.15 mum silicon-on-insulator (SOI) process to extract the results. The comparisons show sufficient agreement between the inductance and quality factor (Q-factor) to be used in design. An amplifier using the inductor models was simulated for the demonstration to show the estimation improvement of the IP3 given by this proposed inductor model.