Realization of high-speed InP SHBTs using novel but simple techniques for parasitic reduction

We have developed novel but simple process techniques for high speed InP SHBTs. For parasitic reduction, the collector layer is undercut using etch-stop layer, base pad is isolated, and emitter metal is widened using thick plated gold. Typical common emitter dc current gain (/spl beta/) and BV/sub CEO/ are about 25 and above 3.5 V, respectively at a collector current density of 1 /spl times/ 10/sup 5/ A/cm/sup 2/. Maximum extrapolated f/sub max/ of 450 GHz with f/sub /spl tau// of 215 GHz is achieved for 0.5 /spl times/ 8 /spl mu/m/sup 2/ emitter area devices at I/sub c/= 17 mA and V/sub CE/ = 1.5 V. These data clearly show that the optimized conventional process can offer the direct implementation of InP HBT for high-speed electronic circuit fabrication.