Proof is in the PTH - assuring via reliability from chip carriers to thick printed wiring boards

The reliability of plated through holes (PTH's) is presented as "PTH life curves" which plot cycle to fail vs. temperature for the entire range of field, accelerated thermal cycling, and assembly reflow thermal exposures on a printed wire board (PWB) or laminate chip carrier (LCC). The curves represent years of testing with the current induced thermal cycle test (CITC) covering different resin systems, via constructions, and metal finishes. The curves reveal a number of critical factors in PTH reliability including the significant effect of Pb free reflows, resin system formulation, and copper plate chemistry on via life. The critical importance of the "assembly life" region of the life curves is presented along with E/SEM photos of a crack opening during a reflow cycle. A finite element model is developed for one of the PTH constructions in this paper to show the complementary use of finite element analysis (FEA) with this approach, since a valid model allows extension of the life data to other design and stress variables. The FEA fatigue life calculations correlated well with the experimental life curves. Examples of cumulative damage life projections for a number of PWB and LCC cases are given using the life curves. Finally, the importance of aggressive monitoring of PTH quality with the CITC 220C test is discussed.