Simulation and measurements on a 64-kbit hybrid Josephson-CMOS memory

A 64-kbit sub-nanosecond Josephson-CMOS hybrid RAM memory is being developed with hybrid high-speed interface circuits. The hybrid memory is designed and fabricated by using commercially available 0.25 /spl mu/m and 0.35 /spl mu/m CMOS processes and the NEC (SRL) 2.5 kA/cm2 and UC Berkeley's 6.5 kA/cm2 Nb processes for Josephson junctions. In order to simulate the low-temperature CMOS circuits, 4 K CMOS device models are established by extracting from experiments. The measurements made at 4 K include static I-V characteristics, gate capacitances and source and drain capacitances. Details of the modeling are found in a companion paper in this issue. Performance of the high-speed interface circuits is optimized by minimizing the parasitic capacitance loading. Both the functional test and high-speed measurement for the interface circuit will be discussed. The whole structure of the memory, including interface circuit, decoder, memory cell, and Josephson read-out circuit is proposed and fabricated. From simulation, a total access time well below 1 ns is expected. The power for the whole system is about 32 mW at 1 GHz. Plans for further power and access time reduction are described.