A PCI target device with re-reusing PCI AD bus

In this paper we bring forward a new technology to re-reuse the PCI AD bus based on the timing sharing reuse technology. It makes the peripheral device can use the PCI AD bus to receive and send data from and to the master device. Though need to design relatively complicated control logic, using the technology to design a chip can approximately reduce 52% of the chip's area. Using 0.35/spl mu/m CHARTERED CMOS technology, the area of the chip is 4.2/spl times/3.7mm/sup 2/.