A design based yield and redundancy model for high density dualport SRAM on 90nm technology

A design based yield and redundancy model for high density dual port SRAM on 90nm technology was presented in this paper. The memory array bitmap and repairability were analyzed from both layout and circuit architecture perspective. The fault signature was categorized by repairing method. The proposed modeling approach allowed direct correlation between circuit architecture and redundancy design thus improved the repair efficiency. The model proved to be valuable for DFY (design for yield) and guided process improvement for yield.