Extremely scaled planar bulk CMOS: challenges and options

Maintaining electrostatic integrity at deeply scaled gate length and improving device transport are two of the lop challenges in extremely scaled planar CMOS technology. For planar bulk CMOS, gate stack scaling continues to be the most effective way of increasing gate control and suppressing short channel effect. However, with the nitrided oxide at the gate leakage limit that circuit designers are willing to tolerate, high-k gate dielectric becomes a necessity for 45 nm node and beyond. To meet performance targets, dual work-function metal gate enhances channel inversion carrier density and gate control by eliminating gate depletion. The ideal gate stack depends on the application: dual work-function metal gate would be required for high performance technology; poly and high-k might be a viable combination for low power products. On the other hand, the importance of carrier transport enhancement is critical if the gate thickness scaling stagnates, or if lithography limitations cause the device gate length to scale less aggressively than the gate thickness. The current activities of device transport improvements focus on channel strain and substrate material engineering. The strain techniques examined range from process induced local strain, e.g., recessed epi-SiGe at S/D, to wafer level global strain, e.g., strain Si on relaxed SiGe virtual substrate. Interesting and promising results and analyses have been reported on even more sophisticated multi-layer heterostructure substrates involving strained SiGe. The talk will give an overview of the challenges mentioned and options for continuing scaling of planar bulk Si CMOS technology.