Switched current integrator for second order sigma delta modulator

In this paper, we present a switched current integrator S21 regulated cascade memory cell techniques for the second order sigma-delta modulator. A structure of offset compensation is used. The simulation result in this layout and in this transistor level is compared. A switched-current integrator is designed with a 0.35 /spl mu/m CMOS process with a 2.5 V power supply. The average low power consumption is 1.25 mW.