Best methods to minimize latch-up sensitivities in semiconductor circuits

Latch-up occurs when two bipolar transistor structures enter a self-sustained low impedance state between the anode and cathode. This condition is often the result of parasitic PNP and NPN structures inherent to CMOS circuits. It is possible to predict the latch-up threshold and therefore exercise sound layout techniques to avoid triggering parasitic SCR structures under normal operating conditions