Sensing design issues in deep submicron CMOS SRAMs

In this paper, solutions to memory design issues in nanometer CMOS are presented. First, a comparative study between various sense-amplifiers is presented in 70nm CMOS technology. Impact of process variation is studied on the performance of these sense-amplifiers. An improved bit-line leakage compensation scheme is proposed to ensure proper sensing in presence of leakage. Performance benefit of up to 68% can be obtained using this technique.