Testing of resistive opens in CMOS latches and flip-flops

Open defects in CMOS memory elements are investigated. The analysis has been carried-out in a class of symmetrical CMOS flip-flop. Main focus is given to high resistive opens in gates. These defects depend on initial conditions prior to the application of the test vectors. Test conditions influencing the detectability of opens in scan path chains are also analyzed. Some sequences of 1's and 0's may fail for detecting opens in gates. Conditions for the input sequences for scan path chains are stated. The dependence of the detectability of opens on the duty cycle is also investigated. Experimental results showing the dependence of the behavior of open gates with the initial conditions are shown.