Analog neural programmable optimizers in CMOS VLSI technologies

Introduces a parallel switched-capacitor (SC) neural optimizer architecture and discusses area limitations due to the incorporation of programmability issues. Due to these limitations this architecture is only suitable for low dimension problems. A serial time-multiplexed architecture which allows digital control on the weight values with reasonable area figures is presented. A 3- mu m CMOS SC prototype demonstrating the concept of SC analog neural optimizers via an integrated circuit is discussed.<
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