Serial block processing for multi-code WCDMA frequency domain equalization

This paper presents an efficient implementation of a frequency domain linear equalizer for WCDMA systems. A significant complexity reduction with respect to traditional equalizers can be achieved by means of frequency domain block processing. After deriving the analytical formulation of the equalizer coefficients, it is shown that the performance of the frequency domain equalizer (FDE) is substantially equivalent to that of the classical time domain equalizer (TDE) over a wide range of operating conditions so that no penalty has to be paid for the complexity reduction. Starting from a pure parallel implementation of the FDE, it is shown that block processing for multi-code downlink WCDMA can be conveniently performed in a serial fashion, through properly reusing small processing elements while exploiting the pipeline in order to reduce the subsequent latency overhead.