Design and FPGA implementation of nonseparable 2-D biorthogonal wavelet transforms for image/video coding

This paper reports on the design and hardware implementation of an efficient architecture for the nonseparable 2-D discrete biorthogonal wavelet transforms (DBWT). The architecture adopts periodic symmetric extension at the image boundaries, therefore it conforms the JPEG-2000 standard. It computes the DBWT decomposition of an NxN image in approximately 2N/sup 2//3 clock cycles (ccs). Hardware implementation results based on a Xilinx Virtex-2000E FPGA chip showed that the processing of 2-D DBWT can be performed at 105 MHz providing a complete solution for the real-time computation of 2-D DBWT with image boundary handling.