A Reconfigurable Co-Processor for Variable Long Precision Arithmetic Using Indian Algorithms

This paper discusses a set of algorithms for performing Variable Long Precision Arithmetic (VLPA) and their implementation on a reconfigurable hardware. These algorithms are characterized by a high degree of similarity, scalability and massive parallelism. Due to these features, a reconfigurable target provides for a reduced design time, easy scalability and the ability to make a cost performance tradeoff. Moreover, similarity in the data path of various algorithms opens the possibility of using partial reconfiguration to reduce the silicon footprint. Performance figures obtained from the implementation compare favorably with that of the GNU multiprecision library. Analysis shows that performance can be enhanced by a deeper pipeline and scaling the width of the data path, with little increase in design complexity, indicating that these algorithms are a promising choice for implementing on a reconfigurable target.