FPGA Implementation of Pipelined On-Line Scheme for 3-D Vector Normalization

A three-dimensional vector normalizer based on pipelined on-line arithmetic is presented. The clock period is kept small by the use of redundant adders and low-precision estimates. The throughput is greatly improved by unfolding and pipelining on-line units and the area is reduced due to left-to-right processing. Assuming the same area/delay metric, the proposed scheme can improve throughput by 89% compared with PROVEN scheme, an ASIC normalizer, and by 10.2× compared with VU, a vector-processing unit for 3-D graphics computing. When implemented as an FPGA-based hardware accelerator, our scheme allows 85% more throughput than VU, and 2.3× more throughput than Pentium III SSE.