A practical packet reordering mechanism with flow granularity for parallelism exploiting in network processors

Network processors (NP) are usually designed to exploit packet level parallelism where system throughput is aggregated by multiple CPU cores. A serious problem in such a system is packet disordering (PD), which may deteriorate network performance greatly. To address the PD problem, a practical reordering mechanism is put forward in this paper. Different from the traditional reordering methods such as in ATM networks, it uses a central-controlled chain-based mechanism to implement packet reordering with flow granularity. We verify it in FPGA and carry out a series of experiments, where the results show that system throughput can be influenced greatly by traffic patterns. We also demonstrate that the reordering with flow granularity is quite requisite in NP, which can increase the system throughput to a great extent compared to the conventional method with global granularity.