Crosstalk improvement technology applicable to 0.14/spl mu/m CMOS image sensor

For pixel crosstalk improvement, modified logic technology with thin epi wafer thickness, thin backend process thickness and air gap guard ring technology, pixel size can be further scaled down to less than 2.8 /spl mu/m /spl times/ 2.8 /spl mu/m and maintain the same performance as 4.0 /spl mu/m /spl times/ 4.0 /spl mu/m pixel does. Greater than 65% crosstalk reduction at 10/spl deg/ incident angle has been demonstrated. This technology can be applicable to CMOS image sensor with 0.14 /spl mu/m design rules.