Impact of oxygen vacancies on high-/spl kappa/ gate stack engineering

The impact of oxygen vacancies in Hf-based gate dielectrics is discussed. Generation of oxygen vacancies in HfO/sub 2/ is thermodynamically driven and causes Si interfacial layer formation and gate Fermi-level pinning in MOS devices. Hence, it is necessary to prevent oxygen transport across both top and bottom gate-dielectric interfaces through careful design of material system and thermal processing steps.