Edge trapping mechanism of current collapse in III-N FETs

Simulations of GaN HFETs using the device simulator DESSIS show, in agreement with our experimental data, that enhanced trapping at both gate edges is responsible for the current collapse. These simulations also show a reduction of the collapse in DHFETs with an InGaN channel, in agreement with our gated transmission line measurements. The results demonstrate that hot electrons play an instrumental role in the collapse process.