Bus-oriented DFT design for embedded cores

This work presents a testable design method for the embedded cores in an object SoC chip. Instead of modifying the digital cores for testability consideration, we target on revising the AMBA bus for test application and response observation. The test information is transformed from a core's I/Os to the chip's external pins. Experimental results on some embedded cores have shown that the proposed method costs small area and timing overhead.