A high-performance 0.5- mu m BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 mu m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. A WSi/sub x/ polycide emitter n-p-n transistor with an emitter area of 0.8*2.4 mu m/sup 2/ provides a peak cutoff frequency (f/sub T/) of 14 GHz with a collector-emitter breakdown voltage (BV/sub CFO/) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f/sub T/ and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process.<
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