IC modeling for yield-aware design with variable defect rates

This paper introduces a modeling methodology that enables design tradeoffs to be performed between yield, throughput and area while targeting process technologies with variable defect rates. A combinatorial model is used to represent candidate circuits in the presence of burn-in component failures, and area and throughput rewards are used for evaluating the expected quality of the final implementation while taking yield issues into consideration. A case study on a benchmark FIR filter design reveals how the methodology can be incorporated into the system design process to evaluate numerous design options implemented on various semiconductor process technologies.