RC-tree delay evaluation in hierarchical environment

An algorithm is presented to compute the delay of an RC-tree network in a hierarchical manner. The RC-tree model is derived from the work of J. Rubinstein and P. Penfield (1983) and T.M. Lin and C. Mead (1984). User-defined storage space, called properties, are used to store partial delay results in the design hierarchy. The delay evaluation becomes very CPU time efficient. This algorithm is well adapted for the evaluation of interconnect wire delay in a hierarchical delay analysis tool. It has been implemented in the authors' hierarchical analysis tool, PREDICT.<
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