The design on RF transceiver at 5 GHz band with package modeling

The paper describes a novel CMOS heterodyne architecture at 5 GHz band which is fabricated in 0.18 /spl mu/m CMOS process operating from a power supply of 1.8 V. We designed the up-mixer, down-mixer and LNA for the 5 GHz band, and the VCO for the 2 GHz band related to our heterodyne architecture. The LPCC 24 pin package is used with package modeling and the 4 key blocks occupy a die area of about 1.5 mm/sup 2/. An off-chip power amplifier is to be used for overall power saving.