Implementation of an LDPC decoder on a vector signal processor

A parallel processor architecture-a vector signal processor (VSP), which consists of independent computation units is presented. This architecture is used to implement the sum-product algorithm to decode low-density parity-check codes. The VSP is well suited for this parallel decoding algorithm which results in a scalable decoder that allows a tradeoff between chip area and data throughput. With increasing number of computation units a data throughput of up to 36.1 MBit per second can be achieved which outperforms existing implementations on digital signal processors.