New implementation for the scalable LDPC-decoders

Trellis decoding of regular and irregular low-density parity-check (LDPC) codes and the corresponding decoder architectures are considered. Moreover, we propose a new approach for computing reliability metrics based on the BCJR algorithm that reduces the message switching activity in the decoder compared to existing approaches. The trellis decoding schedule is employed to decode LDPC codes using constituent soft-input soft-output (SISO) decoders that communicate through interleavers. The proposed tunable schedule exhibits a faster convergence behavior (up to 50% fewer iterations), and hence lower decoding latency, than the commonly employed two-phase schedule, and the corresponding decoder architecture has a significantly reduced memory requirement. Improvement in decoding gain (up to an order of magnitude for moderate-to-high SNR and small number of iterations) is achieved and structural regularity features in the form of permutation matrices further reduce interconnect complexity and improve decoding throughput.