Plan ahead for yield

Time to market has direct impact on the success of our products. A good silicon yield is critical for our production ramp up. A good redundancy plan for yield improvement based on sufficient understanding of the yield model is critical. Memory yield is a primary factor for overall yield. Memories are denser than random logic and prone to defects and low yields. To improve memory yield, redundancy is usually used. As commonly seen in networking silicon designs, our ASICs are memory intensive, as a result memory yield has become a primary factor for overall yield. An efficient redundancy scheme for memory can reduce the impact in terms of area overhead and routing achieve high yield improvement. To achieve good memory yield, plan ahead and plan well. Communication is a key to achieve a successful partnership.