An alternate wire database for Xilinx FPGAs

This paper presents ADB, an alternate wire database, suitable for routing, tracing, and browsing in Xilinx Virtex, Virtex-E, Virtex-II, and Virtex-II Pro FPGAs. While mainstream design flows and place-and-route tools make good use of available routing resources, they often do so at the cost of comparatively large processing times. An alternative scheme is to modify or generate configuration bitstreams directly, in order to achieve more dynamic designs and to reduce processing times and memory footprints. ADB includes a complete set of compact wire databases for the indicated families, and can generate the necessary bitstream configurations with the help of JBits or an independent bitstream interface. These wire databases can also be used in standalone mode to facilitate routing research in situations where real device data might not normally be available.