Ultra-low-voltage robust design issues in deep-submicron CMOS

Design challenges for operating CMOS circuits fabricated in 0.13 /spl mu/m and finer technologies at ultra-low-voltages are analyzed. The design goal consists in minimizing energy by reducing V/sub DD/ while maintaining delay and yield at acceptable levels in the presence of increasing variability of process parameters. First, an estimation model developed to accurately predict operation of bulk- and SOI-CMOS in subthreshold is described. The relation between yield, energy, delay and device parameter distributions is examined next along with tradeoffs necessary to achieve the desired performance point. The main objective of minimizing energy is explored for SRAM cells by predicting the minimum V/sub DD/ based on the data-retention voltage (DRV), and acceptable signal-to-noise margins (SNM). Experimental data from a 4 kB-SRAM test chip in 0.13 /spl mu/m CMOS are presented demonstrating a 90% leakage reduction potential in standby under reduced bias of 250 mV.