High-speed Viterbi decoder for W-LAN and broadband applications

This paper presents a configurable Viterbi decoder implementation that meets the requirements of the IEEE 802.11b and 802.16a standards. The programmable very high-speed integrated circuit hardware description language (VHDL) design supports a constraint length (K) 7 Viterbi decoder realization with code rates (R) of 1/2 and 1/3, and trace-back lengths (TBL) of 35 and 50 symbols. To assure high throughput, an architecture incorporating 32 add compare select (ACS) units operating in parallel has been selected. Circuit simulation results, based on an Altera FPGA, are presented and confirm a throughput of 160 Mbps.