A XiRisc-based SoC for embedded DSP applications

Reconfigurable computing can face many of the current embedded systems design issues, providing a high degree of flexibility and increasing energy efficiency of computation. This paper introduces the architecture of a system on chip for signal processing applications, including an XiRisc reconfigurable processor as the main computational core. This RISC processor features an extensible instruction set, obtained through dynamic reconfiguration of a programmable gate-array embedded as a processor datapath function unit. A prototype chip has been implemented in 0.13 /spl mu/m CMOS technology. The SoC operates at 166 MHz clock speed and the test of several DSP algorithms showed speed-ups ranging from 5/spl times/ to 80/spl times/ with 65%-95% energy savings. As proof of the architectural improvement, energy and area computational efficiency has grown by a factor ranging from 3/spl times/ to 35/spl times/.