BIST controlled variable sense amp timing for 90nm embedded SRAM

Embedded compilable SRAMs, using set sense amp (SSA) timing circuits with variable delays that can be selected during built-in self-test (BIST), are described. The primary purpose of the variable delays is to detect weak cells and AC defects during self test by reducing the "set sense-amp" (SSA) delay, and thereby reducing the signal margin. The weak cells can then be permanently replaced by redundant cells. The variable delay feature is also a powerful characterization tool for new array designs.