A low power capacitive coupled bus interface based on pulsed signaling

A synchronous pulsed signaling system, using on-chip capacitive coupling, for low-power high-speed buses has been implemented in a 0.10-/spl mu/m CMOS DRAM process. We demonstrate 1.0-Gb/s/pair differential pulsed signaling over 10-cm PCB lines with an increased channel 3-dB bandwidth of 2.94 GHz by blocking the driver/receiver capacitances on a bus and eliminating ESD structures. The system dissipates 1.92 mW for both the driver and channel termination at 500 MHz and 1.8-V supply, which is only 1/8 to 1/13 of conventional memory buses using SSTL-2 and RSL.