Triple junctions for reduced impact of offset spacer variation on CMOS device parameters

In this work, we propose a new triple junction approach for aggressively scaled CMOS transistors. It is formed by means of conventional ion implantation in three phases: before offset spacer (LDD), after offset spacer (MDD) and after second spacers (HDD). We demonstrate that the triple junction has great potential in reducing significantly the variation of the device parameters such as drive current, off-state current, and overlap capacitance, originating from the non-uniformity of the offset spacer commonly used in CMOS devices below the 90 nm node.