A new pulsewidth control loop for high-speed VLSI systems

In this paper, we propose a new mechanism for high-speed pulsewidth control loop (PWCL), which a cascade control stage and a differential feedback control voltage are employed to adjust the input signal pulsewidth more efficiently. The detailed comparisons in terms of duty cycle, rising/falling time of the input signal has also been made. The verification of the approach has been performed with HSPICE simulation.