Implementation of a high-performance hardware architecture for binary morphological image processing operations

Development of industrial image processing applications is strictly governed by economical concerns. High demands with respect to recognition speed and certainty have to be satisfied by means of low-cost hardware implementations. Especially realization of such algorithms for extraction of regional information, e.g. for shape recognition, is thus a challenging task. The latter is addressed by investigating the implementability of binary morphological operations with large operator masks. The design procedure for implementation in low-cost FPGAs as well as a relatively accurate estimation of the required hardware effort is presented. Programmable operator mask sizes of up to 31 /spl times/ 31 pixels and a high data throughput of several giga-pixels per second can be obtained by the proposed methods.