A high-speed high-resolution comparator

This paper describes a comparator that not only eliminates offset cancellation capacitors from the signal path in preamplification and latch modes, but also incorporates open loop offset cancellation to cancel the offset of both preamplification stages and the latch. This new architecture effectively increases both speed and resolution. By applying offset cancellation, an offset of less than 800 /spl mu/V at comparison rate of 300 MHz with a 6 mW power dissipation and 3 V power supply has been achieved. The comparator has been extracted and simulated with a 0.35 /spl mu/m HSPICE model.