Targeted layout modifications for semiconductor yield/reliability enhancement

A new layout modification tool for the automation of layout modifications to improve the yield and reliability of semiconductor IC layout is reported. The Peye tool combines a polygon library with the practical extraction and reporting language (Perl). This new tool permits complex layout modification operations to be defined using the powerful language features of Perl. The Peye tool has been interfaced with a sampling-based yield prediction system to enable the measurement of the layout modifications and yield predictions based on these modifications. This enables the usefulness of a modification to a particular design to be assessed by sampling before use. Both the sampled measurement and the final modifications to the whole chip database can be farmed out to a number of networked computers, enabling the system to assess and apply layout modifications to large industrial ICs in a reasonable time. The results of layout modifications are presented.